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 2M x 8 SRAM MODULE
SYS82000RKXC - 70/85/10/12
Issue 1.3 : April 2001 Description The SYS82000RKXC is a plastic 16Mbit Static RAM Module housed in a standard 38 pin Single InLine package organised as 2M x 8 with access times of 85,100, or 120 ns. The module is constructed using four 512Kx8 SRAMs in TSOPII packages mounted onto an FR4 epoxy substrate. This offers an extremely high PCB packing density. The device is offered in standard and low power versions, with the -L module having a low voltage data retention mode for battery backed applications. * * Features Access Times of 85/100/120 ns. Low Power Disapation: Operating 600 mW (Max.) Standby-L Version 1.1 mW (Max.) 5 Volt Supply 10%. Completely Static Operation. Low Voltage VCC Data Retention. On-board Decoding & Decoupling Capacitors. 38 Pin Single-In-Line package (SIP). Upgrade path to SYS84000RKXC (32Mbits).
* * * * * *
Block Diagram
Pin Definition
NC A20 Vcc WE D2 D3 D0 A1 A2 A3 A4 GND D5 A10 A11 A5 A13 A14 A19 CS A15 A16 A12 A18 A6 D1 GND A0 A7 A8 A9 D7 D4 D6 A17 Vcc OE NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
D0 - D7 A0 - A18 OE WE
512K x 8 SRAM
CS
512K x 8 SRAM
CS
512K x 8 SRAM
CS
512K x 8 SRAM
CS
A19 A20 CS
DECODER
Pin Functions
Address Inputs Data Input/Output Chip Select Write Enable Output Enable No Connect Power (+5V) Ground
A0 ~ A20 D0 ~ D7 CS WE OE NC VCC GND
Pin 38 is A21 on the SYS84000RKXC upgrade module.
Package Details Plastic 38 pin Single-In-Line (SIP)
ISSUE 1.3 : April 2001
SYS82000RKXC - 85/10/12
DC OPERATING CONDITIONS Absolute Maximum Ratings
(1)
Parameter
Voltage on any pin relative to VSS Power Dissipation Storage Temperature
Notes :
Symbol
VT PT TSTG
min
-0.3 -55
typ
-
max
+7 4.0 +125
unit
V W o C
(1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply Voltage Input High Voltage Input Low Voltage Operating Temperature
Symbol
VCC VIH VIL TA TAI
min
4.5 2.2 -0.3 0 -40
typ
5.0 -
max
5.5 Vcc+0.3 0.8 70 85
unit
V V V o C o C (I)
DC Electrical Characteristics (VCC=5V10%)
TA 0 to 70OC
Parameter
I/P Leakage Current Output Leakage Current Operating Supply Current Standby Supply Current TTL levels -L Version Output Low Voltage Output High Voltage
Symbol Test Condition
ILI ILO ICC ISB1 ISB2 VOL VOH
min
typ
-
max Unit
4 4 109 12 200 0.4 A A mA mA A V V
VIN = GND to VCC -4 CS = VIH, VI/O = GND to VCC -4 CS = VIL, min cycle, Duty = 100% CS = VIH CS = VCC-0.2V, 0.2 > VIN > VCC-0.2V IOL = 2.1mA IOH = -1.0mA 2.4
Capacitance (VCC=5V10%,TA=25oC)
Note: Capacitance calculated, not measured.
Parameter
Input Capacitance (CS,A19,A20) Input Capacitance (A0-18,OE,WE) I/O Capacitance
Symbol
CIN1 CIN2 CI/O
Test Condition
VIN = 0V VIN = 0V VI/O = 0V
typ
-
max
8 32 10
Unit
pF pF pF
2
SYS82000RKXC - 85/10/12
ISSUE 1.3 April 2001
Operation Truth Table
CS
H L L L
OE
X L X H
WE
X H L H
DATA PINS
High Impedance Data Out Data In High Impedance
SUPPLY CURRENT
ISB1 , ISB2 ICC ICC ICC
MODE
Standby Read Write
Output Disabled
Notes : H = VIH : L =VIL : X = VIH or VIL
AC Test Conditions * Input pulse levels: 0 V to 3.0V * Input rise and fall times: 5ns * Input and Output timing reference levels: 1.5V * Output load: see diagram * VCC = 5V 10%
I/O Pin
Output Load
645 1.76V 100pF
Low Vcc Data Retention Characteristics - L Version Only (TOP = 0C to 70C)
Parameter
VCC for Data Retention
Symbol Test Condition
VDR
CS>VCC-0.2V
min
2.0
-
-L Part typ max
500 -
Unit
V A ns ms
0.2V>Vin>Vcc-0.2 Data Retention Current ICCDR Chip Deselect to Data Ret. Time tCDR Operation Recovery Time tR
VCC=3.0V,CS=VCC-0.2V,0.2V>Vin>Vcc-0.2 See Retention Waveform See Retention Waveform
0 5
3
ISSUE 1.3 : April 2001
SYS82000RKXC - 85/10/12
AC OPERATING CONDITIONS
Read Cycle -85 Parameter Read Cycle Time Address Access Time Chip Select Access Time Output Enable to Output Valid Output Hold from Address Change Chip Selection to Output in Low Z Output Enable to Output in Low Z Chip Deselection to O/P in High Z Output Disable to Output in High Z Symbol tRC tAA tACS tOE tOH tCLZ tOLZ tCHZ tOHZ min 85 10 10 5 0 0 max 85 85 45 30 30 -10 min 100 10 10 5 0 0 max 100 100 50 35 35 -12 min 120 10 10 5 0 0 max Unit 120 120 55 40 40 ns ns ns ns ns ns ns ns ns
Write Cycle
-85
Parameter Write Cycle Time Chip Selection to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output active from end of write Symbol tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW min 85 75 0 75 65 5 0 35 0 5 max 30 -
-10
min 100 80 0 80 70 5 0 40 0 5 max 35 -
-12
min 120 100 0 100 80 5 0 45 0 5 max Unit 40 ns ns ns ns ns ns ns ns ns ns
4
SYS82000RKXC - 85/10/12
ISSUE 1.3 April 2001
Read Cycle Timing Waveform (1,2)
t RC
Address
t AA
OE
t OE t OLZ t OH
CS
t ACS t CLZ (4,5) t OHZ (3)
Don't care.
Dout
Data Valid
t CHZ (3,4,5)
AC Read Characteristics Notes (1) WE is High for Read Cycle. (2) All read cycle timing is referenced from the last valid address to the first transition address. (3) tCHZ and tOHZ are defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. (4) At any given temperature and voltage condition, tCHZ (max) is less than tCLZ (min) both for a given module and from module to module. (5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform(1,4)
tWC
Address
t WR(7)
OE
t AS(6)
t AW t CW
CS
Don't Care
WE
t OHZ(3,9) t WP(2) High-Z t DW tOW
(8)
Dout
High-Z
t DH
Din
Data Valid
5
ISSUE 1.3 : April 2001
SYS82000RKXC - 85/10/12
Write Cycle No.2 Timing Waveform
(1,5)
tWC
Address
t AS(6) t CW t WR(7)
CS
t AW t WP(2)
WE
t WHZ(3,9) t OW High-Z t DW
tOH
(8) (4)
Don't Care
Dout
High-Z
t DH
Din
Data Valid
AC Write Characteristics Notes (1) All write cycle timing is referenced from the last valid address to the first transition address. (2) All writes occur during the overlap of CS and WE low. (3) If OE, CS, and WE are in the Read mode during this period, the I/O pins are low impedance state. Inputs of opposite phase to the output must not be applied because bus contention can occur. (4) Dout is the Read data of the new address. (5) OE is continuously low. (6) Address is valid prior to or coincident with CS and WE low, too avoid inadvertant writes. (7) CS or WE must be high during address transitions. (8) When CS is low : I/O pins are in the output state. Input signals of opposite phase leading to the output should not be applied. (9) Defined as the time at which the outputs achieve open circuit conditions and are not referenced to output voltage levels. These parameters are sampled and not 100% tested.
Data Retention Waveform
Vcc
4.5V
DATA RETENTION MODE
4.5V
t CDR
2.2V
tR
2.2V
V DR
CS > Vcc -0.2V
0V
CS
6
SYS82000RKXC - 85/10/12
ISSUE 1.3 April 2001
Package Information
Dimensions in mm
Plastic 38 Pin Single-In-Line (SIP)
114.12 Max. 3.00 57.00 108.00 3.10 MAX
21.00 Max.
10.00
3.50 +/- 0.50
Ordering Information
SYS82000RKXCLI - 85
Speed 85 10 12 Temperature Range = 85 ns = 100 ns = 120 ns
Blank = Commercial Temperature I = Industrial Temperature Blank = Standard Part L = Low Power Part RKXC = Plastic 38 pin SIP 82000 = 2M x 8 SYS = Static RAM
Power Consumption
Package Organization Memory Type
Note : Although this data is believed to be accurate, the information contained herein, is not intended to and does not create any warranty of merchantibility or fitness for a particular purpose. Our products are subject to a constant process of development. Data may be changed at any time without notice. Products are not authorised for use as critical components in life support devices without the express written approval of a company director.
7
22.00 Max.
18.49


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